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U138F00 — Clock synchronization failure

Clock synchronization failure. The Taycan, 911 (992), Panamera (971), Panamera (972) and Cayenne report this code; below is which control unit sets it on each model and how to read and clear it.

Which models and control units set U138F00

Porsche Taycan

Porsche 911 (992)

Porsche Panamera (971, 2017–2023)

Porsche Panamera (972, 2024–)

Porsche Cayenne (9YA)

How to read and clear U138F00

  1. Plug a standard ENET (Ethernet-to-OBD) cable into your Porsche's OBD port and your Mac or Windows PC.
  2. Open STEUER14, pick your car and run a fault scan: every control unit is read, and U138F00 shows with its status, its full description and the freeze frame when the unit stores one.
  3. Fix the cause first, then clear the fault memory and scan again to check it stays away. Reading and clearing fault codes is free on every control unit.

More about fault memory in the manual →

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Other codes of the DC/DC Converter

U122D00Ethernet databus branch 2, No communication
U12C800MAC address conflict in Ethernet switch branch 1
U12C900MAC address conflict in Ethernet switch branch 2
U12CA00MAC address conflict in Ethernet switch branch 3
U12CB00MAC address conflict in Ethernet switch branch 4
U12D000IPv6 address conflict
U139000Clock synchronization master, branch 1, invalid number
U139100Clock synchronization master, branch 2, invalid number
U13E300CONCLUSION Identification, implausible
U140000Function restriction – supply voltage too low
U140100Function restriction – supply voltage too high
U140800Internal voltage measurement, Implausible signal

All 200 codes of this control unit →

Fault names come from the manufacturer's diagnostic data. STEUER14 is independent and not affiliated with Porsche AG. A code tells you what a control unit detected, not always which part failed — check wiring, supply voltage and related codes before replacing parts. STEUER14 shows each fault's full description, status and freeze frame on the car.